The present invention relates generally to three-axis microelectromechanical systems (MEMS) accelerometers and fabrication methods relating thereto.
Three-axis accelerometers have heretofore been developed for use with motion control instrumentation, laptop computers, gaming consoles and cellular telephones, for example. Generally, such three-axis accelerometers operate based upon either piezoresistive or capacitive acceleration sensing. Capacitive three-axis accelerometers relate to the present invention and a variety of them are disclosed in various patents and publications.
A number of three-axis accelerometers have been patented by Kazuhiro Okada that use piezoresistive or capacitive acceleration sensing. U.S. Pat. No. 4,967,605 discloses a force detector that detects force using resistance elements. The three detector uses “resistance elements having the piezo resistance effect” that “are formed on a single crystal substrate to connect a strain generative body having a supporting portion and a working portion thereto to allow the resistance elements to produce a mechanical deformation on the basis of a displacement with respect to the supporting portion of the working portion, thus to electrically detect a force acting on the working portion.” It is stated in U.S. Pat. No. 4,967,605 that “When a force is applied to the working portion of the force detector according to this invention, there occurs a change in the electric resistance based on mechanical deformation by piezo resistance effect, thus making it possible to electrically detect the three applied.” While the force detector disclosed in U.S. Pat. No. 4,967,605 (and those disclosed by others in U.S. Pat. Nos. 5,485,749 and 6,683,358 B1 and US Patent Application No. US2005/0160814 A1) have a structure that is somewhat similar to the accelerometer disclosed herein, it is actually dissimilar, since the structure is configured to employ piezoresistive elements and is made of a number of bonded substrates.
U.S. Pat. Nos. 5,406,848 and 6,716,253 issued to Okada, and U.S. Pat. No. 5,567,880 issued to Yokota, et. al., a paper entitled “Electrostatic servo system for multi-axis accelerometers” by Jono, et. al., a paper entitled “Three-axis capacitive accelerometer with uniform axial sensitivities” by Mineta, et. al., a paper entitled “Design and processing experiments of a new miniaturized capacitive triaxial accelerometer” by Puers, et. al. and a paper entitled “Five-axis motion sensor with electrostatic drive and capacitive detection fabricated by silicon bulk micromachining” by Watanabe, et. al., for example, disclose three-axis acceleration detectors using capacitive sensing. These detectors have multiple separated substrates with electrodes disposed on them that are used to capacitively sense acceleration.
High volume three-axis accelerometer applications, in particular consumer applications, are extremely performance, cost and size sensitive. For a given set of performance requirements, cost must be reduced through minimizing chip (die) area, simplifying the fabrication process and using standard integrated circuit processes. Minimizing chip area also minimizes the lateral dimensions (i.e., width and length) of the accelerometer chip. However, there are also increasing requirements for minimizing the thickness of the chip, for example for use in very slim cell phones.
The prior art suffers from shortcomings that compromise reduction of cost and size (chip thickness and area) while meeting performance requirements. The prior art embodiments arrange the accelerometer proof mass, the suspension beams and the sense elements in such a way that one or more of the following is compromised: chip size reduction optimization, proof mass increase optimization, suspension beam compliance optimization and/or fabrication process simplification. For example, all of the design embodiments are based on substrate bonding techniques which increase the fabrication cost and chip thickness, if not also the chip area. In many of the design embodiments, the top of the proof mass and the suspension beams are arranged in the same plane, forcing compromises in increasing the proof mass, suspension beam compliance and/or chip size. In some cases where the suspension beams are place in a plane above or below the top or bottom plane of the proof mass to reduce chip area, the fabrication process is complicated and chip thickness is increased because of substrate bonding needs of the design embodiment.
It is also known to those skilled in the art that substrate bonding introduces feature alignment and structural thickness inaccuracies that are larger than those in techniques where all feature alignment is carried out on the same substrate and structural film thicknesses are determined by film deposition. As a result, substrate bonding fabrication techniques often lead to device performance variations that are larger than those resulting from single-substrate substrate fabrication processes.